
==============================================================================
Fast Models 11.25 Base Rev C FVP Release Notes
==============================================================================

------------
Introduction
------------

The Base Rev C platform is an evolution of the Base platform, enhanced
to support exploration of system level virtualization. It is an
Architecture Envelope Model (AEM) which incorporates two AEM clusters,
each of which can be configured with up to four cores. It supports
Armv8 architecture versions through v8.9 and defaults to a configuration
that is compatible with Armv8.0. The model also supports Armv9 features
mentioned below:
 - Realm Management Extension (RME) at Beta quality
 - Scalable Matrix Extension (SME) at Beta quality
 - Scalable Matrix Extension 2 (SME2) at Beta quality
 - Branch Record Buffer Extension (BRBE) at EAC quality
 - Scalable Vector Extension 2 (SVE2) at EAC quality
 - Transactional Memory Extension (TME) at EAC quality

It is freely available and does not require a license from Arm in order
to run the model.

------------
Installation
------------

For installation instructions, see the chapter "Installing Fast Models" in the
Fast Models User Guide:
https://developer.arm.com/documentation/100965/latest/Installing-Fast-Models/Installation

-----------------
What is supported
-----------------

Fast Models FVPs support the following host architectures and operating systems:

For x86 hosts:
* RedHat Enterprise Linux 7
* RedHat Enterprise Linux 8
* Ubuntu 18.04 LTS
* Ubuntu 20.04 LTS
* Windows 10

For aarch64 hosts:
* RedHat Enterprise Linux 8
* Ubuntu 20.04 LTS

When running on Linux, use machines with at least 2GB RAM, and preferably at
least 4GB for best performance.

When running Microsoft Windows 10, use machines with at least 2GB RAM, and
preferably at least 4GB for best performance. To use audio a 2GHz, or faster,
Intel Core2Duo, or similar performing, processor is recommended.

Fast Models Portfolio does not contain the Microsoft Visual Studio
runtime libraries.

The following Visual Studio components are required:
    - Visual C++ ATL for x86 and x64

FVPs shipped with this package are built with Visual Studio 2019 and GCC 9.3.0.


System Level Virtualization
---------------------------

* Additions

This package contains the following additions to the Base Platform
specification:

* A PCIeRootComplex with these address regions:
    * A PCI-E config region at 0x0040000000..0x004fffffff
    * A PCI-E memory region at 0x0050000000..0x005fffffff
    * A PCI-E memory region at 0x4000000000..0x7fffffffff

* An SMMUv3AEM with a control region at 0x002B400000..0x002B4FFFFF

* A DMA330x4 with a control region at 0x002B500000..0x002B5FFFFF

SMMU Combined Interrupt NS is wired to SPI 71
SMMU Combined Interrupt S is wired to SPI 72

PCI INTA is wired to SPI 168
PCI INTB is wired to SPI 169
PCI INTC is wired to SPI 170
PCI INTC is wired to SPI 171
PCI System Error is wired to SPI 175

The SMMUv3 is placed such that accesses to memory by PCI devices acting as bus
masters are affected by it.

The PCI-E config region implements ECAM.

* PCIeRootComplex

This is an abstraction to represent the root of a PCIe device tree.

The addressable regions are also available as the following model parameters:
    * PCIE_CFG_START, PCIE_CFG_END
    * PCIE_MEM0_START, PCIE_MEM0_END
    * PCIE_MEM1_START, PCIE_MEM1_END

Types of PCIe devices:
    * Bridge
        For example Root Port, Switch etc.
    * Endpoint
        For example AHCI_SATA, SMMUv3TestEngine etc.

PCIe device tree:
    * Always has PCIeRootComplex (RC) as its root
    * RC can connect to a Bridge or an EndPoint

PCIe device tree specification:
    * The entire PCIe device tree can be specified through a model parameter `hierarchy_file_name` whose format must be in JSON
    * If none is supplied then a default tree is assumed
    * Start the model and use the MTI trace-source `ROOT_COMPLEX_HIERARCHY` to find out the exact tree and parameter used for each device in the default tree
    * Example usage: `-C TRACE.GenericTrace.trace-sources="FVP_Base_RevC_2xAEMvA.pci.pcie_rc.ROOT_COMPLEX_HIERARCHY"`
    * Briefly, the top-level devices of the default tree are: AHCI_SATA, HOSTBRIDGE, ROOTPORT0, ROOTPORT1, ROOTPORT2, ROOTPORT3, SMMUv3TestEngine0, SMMUv3TestEngine1
    * Please refer to documentation of a specific model to know more about it

Error response from PCIe devices:
    * AMBA SLVERR (TX_ABORT) to PCIe Completer Abort (CA)
    * AMBA DECERR (TX_DECODEABORT) to PCIe Unsupported Request (UR)

* SMMUv3AEM

This is an architectural model implementing the SMMUv3.0 and
SMMUv3.1 architectures which are for I/O virtualization of
devices.

Limitations:
    - No RAS
    - The PMU has limited functionality. Only a subset of the
      architecturally mandatory events are supported (as indicated
      by the SMMU_PMCG_CEID0 fields).  The PMU is only intended for
      demonstration purposes and for driver development.

* Legacy PCI Interrupts

Each PCI device is hardwired to use INTA. That is 1 in the
interrupt_pin register.  This is mandated by the PCI Spec for single
function devices.

The mapping of the interrupts in the bridge follows the prescription
from section 2.2.6 of the PCI Local Bus 3 specification. With

IntA = 0, IntB = 1, IntC = 2, IntD = 3:

BridgeInterrupt = (Device + DeviceInterrupt) % 4


* MSI-X

The model optionally implements MSI-X depending on if a parameter is set. If
this parameter is set then an MSI-X capability is advertised as a PCI
Capability.

Note: The Virtio specification is not fully compliant with the PCI
specification and the virtio block device cannot be used in a 'pure polling'
mode where MSI-X is always masked and only polling the Pending Bit Array is
used.


* Composition

The PCI Subsystem is composed of the following model components:

pci.pcie_rc: This is the PCIeRootComplex which marks the entry into PCIe device tree

pci.pcie_rc.pvbus2pci: This is the bridge from the Programmer's View bus to
the PCI bus.

pci.pci_smmuv3: This is the SMMUv3 architecture model specifically configured for PCIe

pci.dma330x4: A DMA engine capable of initiating memory transactions and interrupts

pci.tbu0_pre_smmu_logger: Logs transactions originating from pci.pcie_rc and pci.dma330x4 and reaching pci.pci_smmuv3

pci.smmulogger: Logs transactions originating from pci.pci_smmuv3

Interesting options are:

pci.pvbus2pci.diagnostics=0x0    # (int) default = '0x0'  : Diagnostics level : [0x0..0x4]
`diagnostics` is a parameter usually available on most PCIe devices.
They get their value from `pci.pcie_rc.diagnostics_level`.
They can be found using the model parameter `--list-params`.

There are two PVBusLoggers in the pvbus2pci component. One in front of the
Configuration space and one in front of the Device space:

pci.pcie_rc.pvbus2pci.devicelogger
pci.pcie_rc.pvbus2pci.cfglogger

There are at least two PVBusLogger(s) in each PCIe device component
    * `dmalogger`: This reports on DMA accesses by the PCI device.
        Example: `pci.pcie_rc.rootport0.dmalogger`
    * `devicelogger`: This reports on bus access made to the PCIe device.
        Example: `pci.pcie_rc.rootport0.devicelogger`

Please use GenericTrace plugin to capture traces from required loggers.
You can use ListTraceSources plugin to list all the available trace sources in a model.

* PCIe Device Assignment

Every PCIe Endpoint can be enabled to support this feature which makes it
assignable to a Trusted Compute Base (TCB).
Once an Endpoint is assigned to a TCB, then it can be configured to
both handle and generate memory transactions to specific memory regions.
Please refer to Arm documentation to know more about this feature.

Current features in the model:

    * DOE read/write mailbox
    * SPDM messages including FINISH_RESPONSE (No encryption of messages yet)
    * IDE capability on device and root-port
    * Secure-SPDM (no MAC, encryption)
    * TDISP messages and state machine

Important parameters to enable this feature in a PCIe RootPort:

    * `rootportda_supported` - Enable Device Assignment features

Important parameters to enable this feature in a PCIe Endpoint:

    * `doe_supported` - Enables PCIe extended capability called
    "Data Object Exchange"
    * `ide_supported` - Enables PCIe extended capability called
    "Integrity and Data Encryption"
        * This parameter also exists on PCIe RootPort
        * The FVP does NOT model any encryption details but will
        respond appropriately for "IDE" request messages
    * `x509_crt_der_filename` - Filename containing a X-509 Certificate issued for this DOE device in DER format
    This certificate should contain the corresponding public-key of the pair containing param <rsa_priv_key_pem_filename>
    * `rsa_priv_key_pem_filename` - Filename containing a RSA private key (in PEM) for this DOE device.
    The corresponding RSA public key should be used to create param <x509_crt_der_filename>
    * `dmtf_meas_spec_info` - Information about DMTF measurement spec format.
    Check DMTF measurement specification format table for more info.
    The content of each line in this file should be in below format
    index_num_in_dec,dmtf_meas_spec_value_type,measurement_filename
    For example:
    0,8,meas1.txt
    1,9,meas2.txt
    10,0,meas3.txt

* Known Limitations

- In a real system use of the stall model would violate PCI timing
  constraints and so should not be used.

* Known Bugs

- Arbitrary sized but naturally aligned accesses to virtio registers via PCI
  are not implemented, the model will print a message if such an access is
  performed.

- Debug reads and writes to the virtio registers are not implemented.

--------------------
Feedback and support
--------------------

Your feedback is important to us, and you are welcome to send us defect reports and
suggestions for improvement on any aspect of the product.

Please visit https://developer.arm.com/support and open a case with feedback or
support issues, using your work or academic email address if possible. Where
appropriate, please provide the following information:
- The product name.
- The product revision or version.
- An explanation with as much information as you can provide. Include symptoms and
  diagnostic procedures if appropriate, and if possible provide an example
  virtual platform that demonstrates the issue you are reporting.

--------------------------------------
Changes in Fast Models 11.25
--------------------------------------

* PCIe topology (or device tree) has moved from being a fixed configuration to a dynamic configuration (based on JSON file).
  Please read the relevant sections on PCIe to know more.

* Based on guidance from our trade compliance team, the crypto plugin (crypto.dll
  and crypto.so) has been removed from the main Fast Models package and placed
  within its own add-on package.
  Contact Arm Support (support@arm.com) for details on downloading this package.

-----------
Limitations
-----------

* RASv2 support for AArch32 is not validated with the Architecture Compliance Kit.

Date:  2024/03/07 18:18:57 GMT
Build: 11.25:15

Confidential

==============================================================================
END
==============================================================================
